Conventionally, screen-type structure elements--for example semiconductor integrated circuit devices such as dynamic RAM with cylindrically formed stack cell capacitors for increasing capacitance--were manufactured by passing through processes such as those shown in FIGS. 43 through 50.
To fabricate the layered structure in FIG. 43, a field SiO.sub.2 film 2 is selectively formed on the main side of a P-type silicon substrate 1 by the known LOCOS method, after which a gate oxide film 5 is formed by a thermal oxidation method. Then the polysilicon in the first layer is stacked by the CVD method (chemical vapor growing method); this is patterned by a photo-etching method to form a polysilicon word line WL. Then N-type impurities (for example arsenic or phosphorous) are implanted in the silicon substrate by an ion-implantation method using word line WL as a mask. Then N.sup.+ semiconductor regions 3 (source region) and 4 (drain region) are formed by the self-alignment method. For insulation, an oxide film 6 is formed in virtually the same pattern on word line WL.
Using the CVD method, an SiO.sub.2 passivation layer 7 is deposited over the entire surface, an Si.sub.3 N.sub.4 layer 8 and an SiO.sub.2 layer 9 for protecting the base layer are successively stacked, and a portion of the stacked film on the N.sup.+ source region 3 is selectively removed by over-cutting using dry etching to form a contact hole 10.
Next, a second layer polysilicon layer 11 is deposited by the CVD method over the entire surface, which includes contact hole 10, to connect with the source region 3, and an SiO.sub.2 layer 12 preform or spacer, which forms a screen-type structure, is deposited on this polysilicon layer 11 by the CVD method.
Next, as shown in FIG. 44, photo-resist 13 is adhered in a prescribed pattern, and patterning is performed using this [photo-resist] as a mask by etching the bottom SiO.sub.2 layer 12.
Next, as shown in FIG. 45, after the removal of photo-resist 13 a third polysilicon layer 13 is deposited over the entire surface of SiO.sub.2 layer 12 and polysilicon layer 11 by the CVD method. This polysilicon layer 13 becomes the screen material.
Next, as shown in FIG. 46, the entire surface of polysilicon layer 13 is etched by dry etching, and polysilicon layer 13 is selectively left by etching back as a side wall on only the outer surface (outer circumference) of SiO.sub.2 layer 12. This polysilicon layer 13 is left in a cylindrical form, and becomes one of the electrodes of the cell capacitor. However, there is quite a large level differential 14 at the time of this etch back due to the word line WL and the stacked films 6, 7, 8, and 9 over it, so that an unetched polysilicon residue 13a remains at the bottom of this level differential.
Next, as shown in FIG. 47, the SiO.sub.2 layer 12 which serves as a preform (spacer) and the stacking film SiO.sub.2 layer 9 are selectively removed by etching, exposing polysilicon layer 13 as a cylinder while forming a fin portion 11A in polysilicon layer 11. However, because the polysilicon residue 13a is not etched, a portion 9a of SiO.sub.2 layer 9 remains at the bottom thereof.
Next, as shown in FIG. 48, a dielectric film, for example Si.sub.3 N.sub.4 layer 15, is deposited over the entire surface by the CVD method, and pinholes are filled with an oxide film by oxidizing the Si.sub.3 N.sub.4 layer, making the dielectric film into a fine film.
Next, as shown in FIG. 49, a fourth layer SiO.sub.2 layer 16 is deposited over the entire surface by the CVD method. This becomes the upper electrode (plate electrode) of the cell capacitor Cap.
Although not illustrated, an inter-layer insulating film is stacked on this upper electrode 16 by the CVD method, and a contact hole which reaches the N.sup.+ drain region 4 is opened therein. A bit line is adhered to this contact hole to manufacture, for example, a memory cell for a 64 megabit dynamic RAM.
By application of "sidewall" technology in this manner, a memory cell having a screen-type structure cylindrical stack cell capacitor Cap can be manufactured, but the present inventors have discovered the following deficiencies upon investigation of this manufacturing method.
That is to say, in the whole-surface etching of polysilicon layer 13 in particular in FIGS. 45 and 46, there is no problem when the base is flat, but as was illustrated, there is a fairly large level differential 14 on the side of word line WL, such that the unetched polysilicon residue 13a remains at the bottom of [that] level differential 14.
This residue 13a, as shown by the diagonal lines in FIG. 50, exists between adjacent capacitors Cap-Cap along word line WL, connecting these capacitors (specifically, between the polysilicon layers 13--13 in the stage shown in FIG. 46). This type of residue 13a also exists similarly in regions outside of what is illustrated.
As a result, capacitor-to-capacitor shorting occurs between each memory cell, causing difficulties such as flawed operation of the memory function, etc., and preventing normal operation.
In circumvention of such problems, polysilicon residue 13a can be completely removed by sufficiently etching the entire surface of polysilicon layer 13 as shown in FIG. 51. In that case, however, there is further etching of the polysilicon layer 13 which one wishes to leave as the lower electrode of the capacitor, and the height thereof is notably reduced.
Since in this case capacitor electrode surface area (in other words, capacitance) is greatly reduced, [such a method] is inappropriate. Furthermore, there are some cases in which, when level differential 14 is even higher, the attempt to remove polysilicon residue 13a will cause the polysilicon layer 13 itself to be excessively etched and disappear.
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which a screen-type structure can be formed controllably and reliably even when the base is not flat.